設計驗證職缺

深耕半導體領域多年，Robert Walters 的客戶橫跨大型跨國集團與台灣知名企業。我們致力於串聯優質企業與專業人才，創造雙贏，立即查看最新設計驗證相關職缺。

篩選結果：

你有 5 個搜尋結果

地區

專業領域

招募類型

全職遠端工作

薪資

產業

經驗

職缺

Design Verification Engineer (Central Flow)

已收藏的職缺

薪資: Negotiable

地區: Hsinchu City

發佈日期: 2025年4月25日

A leading player in the semiconductor industry is seeking an experienced Design Verification Engineer to join their innovative team in Hsinchu. This role is ideal for someone with a strong background in central DV flow development, VIP integration, and collaborative verification processes. The successful candidate will have the opportunity to make a significant impact on cutting-edge projects in a fast-paced, technology-driven environment.

探索更多

Design Verification Engineer

已收藏的職缺

薪資: Negotiable

地區: Hsinchu City

發佈日期: 2025年4月25日

Keywords: Verification, System Verilog, High Speed Interface, Block/System-level Verification Environment Our client is seeking a Design Verification Engineer to join their team in Hsinchu. This role offers an exciting opportunity to develop the NVMe/PCIe Verification environment using System Verilog, verify and debug high-speed interfaces, and build block/system-level verification environments. The successful candidate will be part of a dynamic team that values collaboration, commitment, and understanding.

探索更多

Design Verification Engineer (WLB)

已收藏的職缺

薪資: Negotiable

地區: Hsinchu City

發佈日期: 2025年3月20日

About the Role Our client is seeking a highly skilled DV Engineer to join their dynamic team in Hsinchu. This role provides an exciting opportunity to contribute to top-level or sub-block pre-silicon design verification, covering all aspects from test plan definition to verification coverage analysis. You will work with state-of-the-art methodologies, including SystemVerilog and UVM, while collaborating closely with the validation team to support post-silicon debugging. If you're looking for a challenging and rewarding opportunity in semiconductor verification, this role is for you!

探索更多

Design Verification Engineer-CPU

已收藏的職缺

薪資: TWD2,000,000 - TWD4,000,000 per annum

地區: Hsinchu City

發佈日期: 2025年3月20日

Keywords: Design Verification, CPU Micro-architecture, Test Plan Development, Simulation Methodologies, Formal Verification, Power Intent Verification About the Role We are looking for a Design Verification Engineer to join a leading global technology company. In this role, you will work on cutting-edge CPU projects, verifying design features across various aspects of CPU micro-architecture. This position offers a unique opportunity to collaborate with cross-functional teams and gain deep expertise in simulation, formal verification, and power intent verification. If you are passionate about CPU design and eager to work in an innovative, supportive environment, this is the opportunity for you.

探索更多

Design Verification Engineer

已收藏的職缺

薪資: TWD2,500,000 - TWD5,000,000 per annum

地區: Hsinchu City

發佈日期: 2025年3月20日

Keywords: Digital Design, Verification, Engineer, UVM, ASIC/IC Verification About the Role: Join a leading technology company in Hsinchu as a Design Verification Engineer. This role involves working on cutting-edge digital design projects, focusing on serdes phy IP using UVM. You will play a significant role in the verification of digital designs, from standard spec study and design feature study to co-simulation with analog phy.

探索更多