About the Company
Our client is a semiconductor company developing digital and mixed-signal integrated circuits for a range of computing, consumer electronics, automotive, and networking applications.
The engineering team works across digital and analog design disciplines, applying established ASIC verification methodologies to ensure product functionality, performance, and quality.
About the Company
Our client is a global semiconductor company developing advanced computing solutions. They are looking for a CPU Design Verification Engineer to work with design, verification, and system teams on the development and validation of complex processor architectures.
This role covers functional verification, hardware-software integration, and silicon validation, offering opportunities to work across different stages of the processor development cycle.
Job Summary
We are seeking a Digital Verification Engineer to support the verification of complex digital and mixed-signal designs. The role involves developing verification environments, creating test plans, debugging RTL, and collaborating closely with design teams to ensure functional compliance and product quality. Experience with SystemVerilog, UVM, AMS simulation, and scripting languages is highly preferred.
About the Company
Our client is a global semiconductor company developing advanced ASIC solutions for high-performance networking and connectivity applications. They are seeking an experienced Digital Verification Engineer to contribute to complex chip development projects, working closely with design, architecture, and integration teams to ensure product quality and verification completeness.
Lead Design Verification Engineer – PCIe
📍 Location: Hsinchu
💰 Salary: Competitive and based on experience
Keywords: SystemVerilog, UVM, Design Verification, PCIe, Protocol Stack, Python, Perl, Shell, TCL
Join a high-performing team at the forefront of PCIe IP and SoC innovation. Our client is currently looking for an experienced Lead Design Verification Engineer to take ownership of UVM verification architecture and execution. This is an exciting opportunity to engage in full-lifecycle DV responsibilities, from strategy to silicon, while making a real impact on product quality and verification efficiency.
About the Company
Our client is a growing semiconductor company seeking an experienced Principal Digital Verification Engineer to strengthen its digital design and verification organisation in Hsinchu.
This is a senior technical position responsible for defining and driving verification strategy across complex IP, subsystem, and SoC-level designs. The role will work closely with Architecture, RTL Design, Physical Design, and post-silicon teams to ensure verification quality throughout the development lifecycle.
The position is particularly suited to an experienced verification engineer who combines strong hands-on SystemVerilog/UVM expertise with technical leadership and experience delivering complex ASIC or SoC projects.
