ASIC Design Verification (Ethernet)
About the Role We are looking for an experienced ASIC Design Verification Engineer to join a growing engineering team developing next-generation networking and high-performance connectivity solutions. In this role, you will be responsible for building and executing verification environments for complex ASIC designs, working closely with architecture, design, and system teams throughout the development cycle. This is an excellent opportunity for engineers who enjoy solving challenging verification problems, working on advanced digital IC designs, and collaborating with experienced cross-functional teams.
Key Responsibilities
- Develop verification plans, testbenches, and testcases for ASIC designs at block, subsystem, and chip levels.
- Build and maintain UVM/SystemVerilog-based verification environments.
- Work closely with RTL designers and architects to define verification strategies and achieve coverage closure.
- Perform functional, regression, and system-level verification to ensure design quality.
- Support debugging of pre-silicon and post-silicon issues together with design and system teams.
- Participate in FPGA or emulation validation when required.
- Develop scripts to improve verification efficiency and automate regression flows.
- Review verification methodologies and contribute to continuous process improvement.
- Mentor junior engineers and share verification best practices within the team.
What We're Looking For
- Bachelor's degree or above in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Experience in ASIC/SoC Design Verification using SystemVerilog and UVM.
- Solid understanding of verification methodologies, functional coverage, assertions, and regression flows.
- Experience debugging complex digital designs.
- Familiarity with scripting languages such as Python, Perl, Tcl, or C/C++.
- Strong analytical and problem-solving skills.
- Good communication skills and the ability to work effectively across global engineering teams.
Preferred Experience
Candidates with experience in one or more of the following areas are highly preferred:
- Networking ASIC or switching ASIC verification
- Ethernet switching or packet processing
- L2/L3 networking protocols
- TCP/IP, VLAN, QoS, TSN or tunneling protocols
- FPGA or hardware emulation
- High-speed connectivity or datacenter networking products
Why Join
- Work on advanced ASIC development projects for next-generation networking products.
- Collaborate with experienced design and architecture teams in a highly technical environment.
- Gain exposure to complete SoC development from architecture through silicon validation.
- Opportunities for technical growth, ownership, and career development within a global engineering organization.
關於職缺
招募類型: 永久性
專業領域: 半導體
職務類別: 設計驗證
產業: 工程
薪資: Negotiable
辦公模式: 實體辦公模式
經驗: 專員
地區 Hsinchu City
FULL_TIME職務參考: KQZCZT-8FCDD02A
發佈日期: 2026年7月24日
獵頭顧問 Joanne Chen
taipei semiconductor/design-verification 2026-07-24 2026-09-22 engineering Hsinchu City TW Robert Walters https://www.robertwalters.com.tw https://www.robertwalters.com.tw/content/dam/robert-walters/global/images/logos/web-logos/square-logo.png true