Our industry specialists will listen to your aspirations and share your story with the most prestigious organisations in Taiwan. Together, let’s write the next chapter of your career.
For Robert Walters Taiwan, recruitment is more than just a job. We understand that behind every opportunity is the chance to make a difference to people’s lives
Our industry specialists will listen to your aspirations and share your story with the most prestigious organisations in Taiwan. Together, let’s write the next chapter of your career.
For Robert Walters Taiwan, recruitment is more than just a job. We understand that behind every opportunity is the chance to make a difference to people’s lives
Robert Walters has built a strong reputation across Taiwan for placing professionals into semiconductor industry. View our latest design verification jobs here.
Lead Design Verification Engineer – PCIe
📍 Location: Hsinchu
💰 Salary: Competitive and based on experience
Keywords: SystemVerilog, UVM, Design Verification, PCIe, Protocol Stack, Python, Perl, Shell, TCL
Join a high-performing team at the forefront of PCIe IP and SoC innovation. Our client is currently looking for an experienced Lead Design Verification Engineer to take ownership of UVM verification architecture and execution. This is an exciting opportunity to engage in full-lifecycle DV responsibilities, from strategy to silicon, while making a real impact on product quality and verification efficiency.
A leading player in the semiconductor industry is seeking an experienced Design Verification Engineer to join their innovative team in Hsinchu. This role is ideal for someone with a strong background in central DV flow development, VIP integration, and collaborative verification processes. The successful candidate will have the opportunity to make a significant impact on cutting-edge projects in a fast-paced, technology-driven environment.
About the Role
Join a leading technology company in Hsinchu as a Design Verification Engineer and take part in verifying high-performance SerDes PHY IP. You will work with a collaborative team, using advanced verification methodologies and tools, while enjoying flexible work arrangements, training programs, and a culture that values growth and knowledge sharing.
Keywords: Design Verification, CPU Micro-architecture, Test Plan Development, Simulation Methodologies, Formal Verification, Power Intent Verification
About the Role
We are looking for a Design Verification Engineer to join a leading global technology company. In this role, you will work on cutting-edge CPU projects, verifying design features across various aspects of CPU micro-architecture. This position offers a unique opportunity to collaborate with cross-functional teams and gain deep expertise in simulation, formal verification, and power intent verification. If you are passionate about CPU design and eager to work in an innovative, supportive environment, this is the opportunity for you.
Overview
A leading semiconductor IP company is seeking a Design Verification Engineer to join its growing team in Hsinchu. You will work on high-quality IP products used by global IC design houses and foundries, contributing to verification of advanced interface protocols in a collaborative and inclusive environment.
Overview
We are looking for a Senior Digital Verification Engineer to join a collaborative semiconductor design team. This role focuses on top-level and block-level digital verification for advanced digital and mixed-signal designs, working closely with design engineers to ensure full functional compliance and high-quality delivery.
Responsibilities
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Lead and manage digital verification environments for complex semiconductor designs
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Define verification methodologies, review specifications, and develop comprehensive test plans
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Perform RTL review, debug simulation issues, and resolve functional bugs
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Design digital sub-blocks and support system-level integration
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Develop analog models using Cadence Virtuoso and support mixed-signal verification
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Create block-level and system-level SystemVerilog assertions
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Import and enhance existing UVM environments to improve verification efficiency
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