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服務項目

我們為企業量身打造招募解決方案,以其快速、有效深受臺灣頂尖企業信賴。瀏覽由Robert Walters臺灣提供的各種客製化服務與資源。

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真正具有國際視野並深耕在地市場的招募機構,我們服務臺灣市場超過 10 年,並在臺北設有完善的辦公室。

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Sr. Design Verification Engineer (TPE)

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About the Company Our client is a semiconductor company developing digital and mixed-signal integrated circuits for a range of computing, consumer electronics, automotive, and networking applications. The engineering team works across digital and analog design disciplines, applying established ASIC verification methodologies to ensure product functionality, performance, and quality.

Key Responsibilities

  • Develop comprehensive verification plans based on design specifications, requirements, and product documentation for digital and mixed-signal ICs.

  • Collaborate with digital and analog design engineers to establish system-level verification strategies and behavioural models.

  • Develop and maintain verification environments using SystemVerilog and UVM.

  • Create test cases, assertions, checkers, and test scenarios to verify design functionality and ensure specification compliance.

  • Analyse simulation results and debug design issues using code coverage and functional coverage metrics.

  • Develop reusable verification IPs, test environments, checkers, and verification components to improve team efficiency.

  • Automate verification workflows and repetitive tasks using scripting languages such as TCL and Python.

  • Perform gate-level simulation and verification to evaluate design behaviour under timing-related conditions.

  • Prepare verification documentation, test reports, and review materials to support project execution.

  • Work with industry-standard ASIC tools, including digital simulators, coverage analysis platforms, and formal verification tools.

Requirements

  • M.S. degree in Electrical Engineering or a related discipline, with 5–8 years of experience in digital ASIC verification.

  • Strong understanding of ASIC design and development flows, digital design concepts, and verification methodologies.

  • Proficiency in SystemVerilog and UVM, with experience developing verification environments and test cases.

  • Familiarity with RTL and behavioural modelling for digital or mixed-signal designs.

  • Hands-on experience with functional coverage, code coverage, assertions, and verification debugging.

  • Experience with gate-level simulation and formal verification methodologies is an advantage.

  • Knowledge of communication protocols such as I2C, I3C, SPI, USB, and PMBus is preferred.

  • Proficiency in scripting languages such as TCL or Python; C/C++ programming experience is an advantage.

  • Exposure to embedded systems or firmware development is a plus.

  • Experience in power management IC applications or related semiconductor products is beneficial.

  • Strong analytical, problem-solving, and communication skills, with the ability to collaborate effectively across multidisciplinary engineering teams.

What's Next?

If you have solid experience in digital ASIC verification and are interested in working on digital and mixed-signal IC development, we welcome your application.

招募類型: 永久性

專業領域: 半導體

職務類別: 設計驗證

產業: 工程

薪資: TWD2,500,000 - TWD3,800,000 per annum

辦公模式: 實體辦公模式

經驗: 專員

地區 Taipei

職務參考: 1DH917-82342A4E

發佈日期: 2026年11月4日

獵頭顧問 Joanne Chen

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