Senior/ Principal Design Verification (CPU/GPU)

About the Company Our client is a growing semiconductor company seeking an experienced Principal Digital Verification Engineer to strengthen its digital design and verification organisation in Hsinchu. This is a senior technical position responsible for defining and driving verification strategy across complex IP, subsystem, and SoC-level designs. The role will work closely with Architecture, RTL Design, Physical Design, and post-silicon teams to ensure verification quality throughout the development lifecycle. The position is particularly suited to an experienced verification engineer who combines strong hands-on SystemVerilog/UVM expertise with technical leadership and experience delivering complex ASIC or SoC projects.

Key Responsibilities

• Define and drive verification strategies across block, subsystem, and SoC levels.

• Develop comprehensive verification plans, methodologies, milestones, coverage targets, and signoff criteria.

• Lead the architecture and development of scalable SystemVerilog/UVM verification environments.

• Drive constrained-random verification, functional coverage, assertions, code coverage, regression, and coverage closure.

• Develop and review SystemVerilog Assertions (SVA) for design validation and protocol checking.

• Lead complex SoC-level debugging and root-cause analysis across verification and design environments.

• Support advanced verification activities including CDC/RDC, low-power verification, gate-level simulation, formal verification, lint, reset, and clocking validation.

• Perform and support GLS with SDF annotation, including timing-related and X-propagation debugging.

• Work closely with RTL engineers to identify design issues and improve design-for-verification methodology.

• Collaborate with Architecture teams to translate functional and system requirements into effective verification strategies.

• Partner with Physical Design teams on timing-related verification and implementation issues.

• Support post-silicon bring-up, validation, and debugging where required.

• Develop reusable verification components and methodologies to improve efficiency across projects.

• Improve regression infrastructure, verification automation, and debugging workflows.

• Provide technical leadership and mentoring to verification engineers while establishing engineering best practices.

• Communicate verification progress, coverage status, technical risks, and readiness to relevant stakeholders.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.

• Approximately 12+ years of experience in ASIC/SoC digital verification, with experience delivering complex semiconductor products through tapeout.

• Strong hands-on expertise in SystemVerilog and UVM.

• Extensive experience developing verification environments, test plans, testbenches, constrained-random stimulus, and reusable verification components.

• Strong knowledge of SVA, functional coverage, code coverage, regression management, and coverage closure.

• Experience debugging complex IP, subsystem, or SoC-level verification issues.

• Familiarity with mainstream simulation and debugging tools such as VCS, Xcelium, or Verdi.

• Strong understanding of CDC/RDC, clock/reset architecture, and cross-domain verification.

• Experience with gate-level simulation (GLS), SDF annotation, and timing-related debugging.

• Knowledge of low-power verification methodologies, including UPF or equivalent approaches.

• Familiarity with formal verification, linting, and other static verification methodologies.

• Demonstrated ability to provide technical leadership or mentoring within a verification team.

• Strong analytical, debugging, and cross-functional communication skills.

• Good written and spoken English.

Experience with large-scale computing, processing, AI, networking, multimedia, or other complex SoC architectures would be advantageous.

Additional experience with emulation, post-silicon validation, performance verification, or scripting languages such as Python/TCL is also beneficial.

The Opportunity

This role provides significant technical ownership across the digital verification lifecycle, from verification architecture and methodology development through coverage closure, tapeout, and post-silicon support.

You will have the opportunity to influence verification strategy for complex SoC designs while working closely with architecture, design, implementation, and validation teams.

The position offers a strong combination of hands-on technical depth and verification leadership, making it suitable for senior engineers looking to take broader ownership of complex semiconductor development programmes.

What's Next

If you have extensive ASIC/SoC verification experience and enjoy solving complex verification challenges while providing technical leadership to engineering teams, we welcome your application.