Design Verification Engineer (Taipei)
Position: Senior Functional Verification Engineer – SoC & High-Speed Interfaces Location: Taipei Join a fast-growing semiconductor company that powers next-gen multimedia and secure computing platforms. We’re hiring a seasoned verification engineer passionate about functional quality and real-world impact. In this role, you’ll take the lead on verifying multimedia and networking IPs—HDMI, DP, MAC, Video Codec, and Security modules—while collaborating with a cross-functional global team.
Responsibilities:
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Lead SoC and IP-level functional verification using UVM
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Collaborate with RTL designers, system architects, and firmware teams
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Validate protocols and ensure compliance with industry standards
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Develop reusable verification components and automation flows
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Ensure first-silicon success by driving verification completeness
Requirements:
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5+ years in digital or SoC DV
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Strong experience in SystemVerilog/UVM and functional coverage
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Familiarity with AXI/APB and high-speed interface protocols
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Bonus: exposure to Spyglass Lint/CDC/RDC, Python automation, or compliance test
關於職缺

招募類型: FULL_TIME
專業領域: 半導體
職務類別: 設計驗證
產業: 工程
薪資: Negotiable
辦公模式: 實體辦公模式
經驗: 專員
地區 Taipei
FULL_TIME職務參考: O78S73-694CCF0F
發佈日期: 2025年5月23日
獵頭顧問 Joanne Chen
taipei semiconductor/design-verification 2025-05-26 2025-07-22 engineering taipei TW Robert Walters https://www.robertwalters.com.tw https://www.robertwalters.com.tw/content/dam/robert-walters/global/images/logos/web-logos/square-logo.png true