Principal Engineer Computer-Aided Design

Principal Engineer Computer-Aided Design Salary: Competitive and based on experience Location: Hsinchu Keywords: collaborative, supportive, dependable, knowledgeable, inclusive, interpersonal, enthusiastic, flexible working opportunities, training opportunities

A leading global technology organisation is seeking a Principal Engineer Computer-Aided Design to join their team in Hsinchu. This role offers you the opportunity to work at the forefront of physical verification and design, supporting worldwide teams and contributing to the development of advanced electronic design automation solutions. You will be part of a supportive network where your expertise in EDA methods, layout rules, and device engineering will be highly valued. The organisation is committed to fostering an inclusive environment with flexible working opportunities and ongoing training, ensuring you can grow both professionally and personally. If you are passionate about collaborating with talented engineers and making a meaningful impact on device quality and reliability, this is the perfect opportunity for you.

• Join a globally recognised technology leader in Hsinchu, offering flexible working opportunities and a commitment to professional growth through extensive training programmes.
• Work closely with international teams, sharing your knowledge and supporting layout verification activities across remote sites worldwide, ensuring high standards of quality and reliability.
• Be part of an inclusive and supportive environment where your interpersonal skills and enthusiasm for collaborative problem-solving are celebrated, allowing you to thrive as a Principal Engineer Computer-Aided Design.

What you'll do:

As a Principal Engineer Computer-Aided Design based in Hsinchu, you will play a pivotal role in advancing the organisation’s physical verification capabilities. Your day-to-day responsibilities will involve developing regression test cases for QA purposes, supporting engineers with sophisticated verification tools, and applying your deep knowledge of EDA methods to address specialised needs such as ESD and ERC. You will collaborate extensively with technology development teams to refine DRC rules and manufacturability checks while designing rule decks that streamline workflows. Your expertise will be instrumental in verifying foundry rule decks, supporting global sites with layout verification tasks, and resolving complex issues efficiently. By working together with a diverse team focused on improving device quality and reliability, you will contribute significantly to the organisation’s success while enjoying opportunities for personal growth within an inclusive environment.

• Develop comprehensive physical verification regression test cases to ensure the highest quality assurance standards for physical verification decks.
• Provide expert support to Layout and Design engineers by guiding them through physical verification activities using industry-leading tools such as Siemens Calibre, Cadence Pegasus, or Synopsys Hercule.
• Utilise your advanced understanding of electronic design automation methods to assist with ESD, ERC, Voltage-Aware DRC, via doubling methodologies, and other specialised verification processes.
• Collaborate closely with Technology Development and Device Engineering teams to create robust DRC rules, introduce additional devices, and implement design for manufacturability checks.
• Design rule decks as required to optimise workflow efficiency and support seamless integration within the verification process.
• Verify foundry rule decks thoroughly and enhance them to meet evolving industry standards and project requirements.
• Offer dependable support to remote sites around the globe by assisting with layout verification activities and troubleshooting complex issues.
• Lead efforts in debugging physical verification challenges, ensuring swift resolution and continuous improvement in device performance.
• Work collaboratively as a valued member of a team dedicated to developing innovative flows that elevate the quality and reliability of devices.

What you bring:

Your background as a Principal Engineer Computer-Aided Design will showcase extensive experience in PDK development within the semiconductor sector. You bring fluency in key industry formats such as SVRF and TVF alongside accomplished debugging skills that enable you to resolve intricate physical verification challenges. Your familiarity with customising Calibre Interactive ensures streamlined processes for layout engineers while your solid grasp of layout rules, device identification concepts, and foundry regulations supports robust design outcomes. Proficiency in Cadence Virtuoso and CalibreDRV further enhances your capability to manage complex projects efficiently. Experience leveraging AI solutions demonstrates your commitment to innovation within EDA environments. Above all, your excellent English communication skills combined with strong interpersonal abilities make you an invaluable collaborator who thrives in multicultural settings.

• Over five years’ proven experience developing and supporting Process Design Kit activities within the semiconductor industry.
• Fluency in SVRF (Standard Verification Rule Format) and TVF (Technology Verification Format), enabling you to manage complex verification tasks effectively.
• Demonstrated ability in debugging physical verification issues with precision and thoroughness.
• Familiarity with customising Calibre Interactive for enhanced user experience during layout verification processes.
• Comprehensive knowledge of layout rules, device identification concepts, and foundry rules essential for successful CAD engineering.
• Expertise in Cadence Virtuoso and CalibreDRV tools for efficient design management and verification.
• Experience utilising AI solutions within electronic design automation environments to optimise workflows.
• Excellent English verbal and written communication skills paired with strong interpersonal abilities for effective collaboration across global teams.