Design Verification (Ethernet Switch)

About the Company Our client is a global semiconductor company developing advanced ASIC solutions for high-performance networking and connectivity applications. They are seeking an experienced Digital Verification Engineer to contribute to complex chip development projects, working closely with design, architecture, and integration teams to ensure product quality and verification completeness.

Key Responsibilities

• Develop and maintain testbenches, testcases, and verification environments for complex ASIC designs at module, subsystem, and system levels.

• Collaborate with architecture and RTL design teams to review microarchitecture, define verification strategies, and drive verification closure.

• Apply SystemVerilog, UVM, SVA, and coverage-driven verification methodologies to ensure comprehensive functional verification.

• Support design integration and debugging activities throughout pre-silicon verification and post-silicon validation.

• Verify networking-related functions, including packet classification, forwarding, buffer management, queuing, scheduling, and Quality of Service (QoS).

• Investigate complex design and system-level issues, identify root causes, and work with cross-functional teams to implement solutions.

• Participate in emulation and FPGA-based validation activities where applicable.

• Develop scripts and automation tools using languages such as C/C++, Tcl, or Perl to improve verification efficiency.

• Work closely with design and integration teams to resolve issues and maintain verification quality throughout the development cycle.

• Share technical knowledge and provide guidance to less experienced engineers when required.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.

• Approximately 5+ years of experience in ASIC digital verification, with relevant experience in networking or other complex digital ASIC designs.

• Strong hands-on experience with SystemVerilog, UVM, SVA, and coverage-driven verification.

• Solid understanding of Ethernet switching or networking-related ASIC architecture and packet processing.

• Familiarity with packet classification, forwarding pipelines, buffer management, queuing, scheduling, and QoS mechanisms.

• Knowledge of networking protocols and technologies such as Ethernet, VLAN, TCP/IP, and Layer 2/Layer 3 forwarding.

• Experience in pre-silicon debugging and system-level problem-solving; post-silicon validation experience is an advantage.

• Familiarity with emulation, FPGA validation, or hardware-assisted verification is beneficial.

• Scripting or programming experience in C/C++, Tcl, Perl, or similar languages is a plus.

• Strong communication and collaboration skills, with the ability to work effectively across engineering teams in Chinese and English.

• Ability to manage technical challenges and project timelines while maintaining verification quality.

What's Next

If you have solid ASIC verification experience and a strong interest in networking or complex digital systems, we welcome your application. This role offers the opportunity to work on advanced semiconductor designs and collaborate with experienced engineers across the development lifecycle.