Sr. Design Verification Engineer

Job Summary We are seeking a Digital Verification Engineer to support the verification of complex digital and mixed-signal designs. The role involves developing verification environments, creating test plans, debugging RTL, and collaborating closely with design teams to ensure functional compliance and product quality. Experience with SystemVerilog, UVM, AMS simulation, and scripting languages is highly preferred.

Key Responsibilities

• Develop and maintain block-level and system-level verification environments.
• Create verification plans, test cases, and coverage strategies based on design specifications.
• Debug RTL and simulation issues, perform root cause analysis, and drive issue resolution.
• Collaborate with design teams to ensure design functionality and verification completeness.
• Develop SystemVerilog assertions and verification models for digital and mixed-signal applications.
• Enhance and reuse UVM-based verification environments across multiple projects.
• Automate verification flows using scripting languages such as Python, TCL, or Shell.
• Support mixed-signal verification and analog model integration when required.

Requirements

• BS/MS in Electrical Engineering or related field.
• 3+ years (MS) or 5+ years (BS) of digital verification experience.
• Strong experience with SystemVerilog and UVM methodologies.
• Experience with RTL debugging, simulation analysis, and verification planning.
• Familiarity with mixed-signal verification, AMS simulation, or analog behavioral modeling is a plus.
• Experience with Cadence verification tools is preferred.
• Proficiency in Python, TCL, Shell, or other automation scripting languages.
• Strong communication skills and ability to work in cross-functional engineering teams.