Sr. Design Verification Engineer

About the role A technology company is seeking a Senior Digital Design Verification Engineer to join its hardware team in Taipei. You will focus on verifying complex digital designs and high-speed IPs used in performance-critical systems, working closely with design and architecture teams.

What you’ll do

• Lead digital design verification using SystemVerilog and UVM
• Verify high-speed IPs such as PCIe, Ethernet, Switch, or communication interfaces
• Develop testbenches, regression flows, and coverage-driven verification plans
• Debug functional issues and analyze protocol-related problems
• Create automation scripts to improve verification efficiency
• Review specifications and translate them into verification strategies
• Collaborate with design, FPGA, and architecture teams throughout development
• Document results and support continuous process improvement

What you bring

• 5+ years of experience in digital design verification
• Strong hands-on experience with SystemVerilog and UVM
• Experience with high-speed interfaces (PCIe, Ethernet, MIPI, Switch, etc.)
• Scripting skills in Python, Perl, or similar languages
• Familiarity with FPGA-based systems is a plus
• Strong debugging, analytical, and communication skills
• Bachelor’s or Master’s degree in EE, CS, or related field

What’s on offer

• Opportunity to work on high-performance hardware systems
• Collaborative and technically strong engineering team
• Exposure to advanced FPGA and low-latency technologies
• Competitive compensation and career growth opportunities