Design Verification Engineer (PCIE)

Lead Design Verification Engineer – PCIe 📍 Location: Hsinchu 💰 Salary: Competitive and based on experience Keywords: SystemVerilog, UVM, Design Verification, PCIe, Protocol Stack, Python, Perl, Shell, TCL Join a high-performing team at the forefront of PCIe IP and SoC innovation. Our client is currently looking for an experienced Lead Design Verification Engineer to take ownership of UVM verification architecture and execution. This is an exciting opportunity to engage in full-lifecycle DV responsibilities, from strategy to silicon, while making a real impact on product quality and verification efficiency.

Why this role stands out:

• Senior role focusing on state-of-the-art PCIe IP and SoC product lines

• Ownership of system- and unit-level UVM verification environments

• Direct influence on DV strategy, coverage, and silicon debug

• Based in Hsinchu, with a global leader in the semiconductor sector

Your Role:

As a Lead DV Engineer, you’ll be responsible for both the technical architecture and execution of verification environments. You’ll define strategies with architects, build reusable testbenches, perform coverage analysis, and troubleshoot issues from simulation through silicon validation. You’ll also drive process improvements and initiatives aimed at raising both efficiency and IP quality.

Key Responsibilities:

• Architect and implement system/unit-level UVM environments for PCIe IP and SoC designs

• Collaborate with design teams and architects to define DV strategy and execution roadmap

• Analyze coverage (functional, code, and test plan), and optimize for sign-off readiness

• Debug silicon issues and drive root cause analysis with corrective action plans

• Introduce and execute initiatives to improve IP quality and verification productivity

Your Background:

You’re a seasoned verification engineer with a strong foundation in SystemVerilog and object-oriented programming. You’ve worked extensively with UVM and PCIe protocols, and you're comfortable navigating complex DV environments independently. You're passionate about producing robust IP and improving processes at scale.

Required Qualifications:

• Master’s degree in Electrical Engineering or a related discipline

• 5+ years of hands-on industry experience in ASIC/SoC Design Verification

• Proficient in SystemVerilog and OOP concepts

• Experience with UVM, SVA, DPI, and VIPs

• Familiarity with the PCIe protocol stack is essential

• Proficient in at least one scripting language (Python, Perl, Shell, Tcl)

• Solid understanding of DV methodologies and best practices

What Makes This Company Different:

Our client is a trusted name in the semiconductor industry, known for its high-performance IP solutions and engineering excellence. With an emphasis on professional development, work-life flexibility, and inclusive culture, they offer a supportive environment where top engineers can thrive. Career progression, internal mentorship, and continuous learning are integral to their team philosophy.

What’s Next?

Ready to step into a role where your technical leadership can shape next-generation IP products?

👉 Apply now and take the lead in defining excellence in design verification.