Firmware Design Verification Engineer

We are seeking a High-Speed PHY Validation Engineer focusing on post-silicon characterization for High-Speed SerDes/Interface IPs. With a "software-defined hardware" mindset, you will bridge hardware measurement and automation by architecting Python frameworks to control PHY registers and lab instruments, ensuring the signal integrity and reliability of our cutting-edge chips.

• Post-Silicon Validation: Lead the characterization and validation of High-Speed Interface IPs (e.g., SerDes, PCIe, USB, or MIPI) to ensure performance meets specifications.

• Automation Framework Development: Design and implement automated test environments using Python to control lab instruments (BERT, Oscilloscopes) and chip registers for high-efficiency data collection.

• PHY Tuning & Debugging: Collaborate with Analog/Digital designers to perform PHY-level tuning and troubleshoot signal integrity (SI) issues at the post-silicon stage.

• Validation Strategy Definition: Define comprehensive test plans covering various PVT corners and jitter tolerance testing.

• Data Analysis & Tool Development: Develop internal tools to analyze validation datasets and generate visualized reports for design optimization.