Senior Digital Design Verification Engineer

Working as a Senior Digital Design Verification Engineer based in Hsinchu

Key Responsibilities:

• Defining the verification plan in cooperation with chip lead, AMS verification and application engineers
• Developing the UVM simulation environment: drivers, monitors, checkers, assertions and score board
• Working with WREAL behavior models for analog functions provided by AMS verification team
• Developing and running top-level simulations according to the verification plan
• Preparing and holding design verification reviews
• Creating and maintaining regression test suites
• Involve in defining and driving design and verification methodologies

Key Requirements:

• BSEE and 5+ years of verification / design experience
• Experience in mixed signal / co-simulation (analog, digital) and UVM verification methodologies
• Experience in writing verification plans, creating test benches and automating regression test suites, preparing and presenting detailed verification reviews
• Experience in working with behavioral models for analog IPs (both event-driven and conservative)
• Understand and debug digital RTL and analog schematics
• Working knowledge of state of the art EDA tools
• Strong background in design and verification languages and methodologies (e.g. Verilog, System Verilog, UVM)
• Solid scripting skills (Python or Perl or TCL)
• Fluent in English. Ideally, experience in promoting verification methodology, strategies and collaboration work with a global team
• 3+ years' experience verifying mixed-signal