Senior Digital Design Verification Engineer
Location Hsinchu CityFULL_TIME
Consultant Joanne Chen
Job Ref 1135270/001
Date posted 24 May 2022taipei tech-transformation/development-programming 2022-05-24 2022-07-23 engineering Hsinchu City TW Robert Walters https://www.robertwalters.com.tw https://www.robertwalters.com.tw/content/dam/robert-walters/global/images/logos/web-logos/square-logo.png
Working as a Senior Digital Design Verification Engineer based in Hsinchu
- Defining the verification plan in cooperation with chip lead, AMS verification and application engineers
- Developing the UVM simulation environment: drivers, monitors, checkers, assertions and score board
- Working with WREAL behavior models for analog functions provided by AMS verification team
- Developing and running top-level simulations according to the verification plan
- Preparing and holding design verification reviews
- Creating and maintaining regression test suites
- Involve in defining and driving design and verification methodologies
- BSEE and 5+ years of verification / design experience
- Experience in mixed signal / co-simulation (analog, digital) and UVM verification methodologies
- Experience in writing verification plans, creating test benches and automating regression test suites, preparing and presenting detailed verification reviews
- Experience in working with behavioral models for analog IPs (both event-driven and conservative)
- Understand and debug digital RTL and analog schematics
- Working knowledge of state of the art EDA tools
- Strong background in design and verification languages and methodologies (e.g. Verilog, System Verilog, UVM)
- Solid scripting skills (Python or Perl or TCL)
- Fluent in English. Ideally, experience in promoting verification methodology, strategies and collaboration work with a global team
- 3+ years' experience verifying mixed-signal
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