Sr. DFT Engineer

Key Responsibilities * Lead frontend and Design for Test (DFT) implementation for wireless SoC products * Develop and optimise low-power frontend flows, including synthesis, static timing analysis (STA), timing/power closure, and PPA optimisation (22nm and below) * Drive synthesis, formal verification, DFT, and STA processes throughout the SoC development lifecycle * Plan and execute DFT integration including SCAN, ATPG, and MBIST strategies * Collaborate with digital, analog, and physical design teams to enhance RTL-to-netlist implementation quality * Implement low-power design methodologies using UPF * Interface with product engineering and test engineering teams to align test strategies and silicon validation requirements * Support functional and gate-level debugging to ensure high-quality silicon delivery * Contribute to continuous improvement of frontend and DFT methodologies

Requirements

• Strong experience in synthesis, formal verification, and static timing analysis using industry-standard tools (e.g., Synopsys)

• Proficiency in RTL design and simulation using Verilog/SystemVerilog

• Hands-on experience with DFT methodologies including ATPG and MBIST (e.g., Tessent toolsets)

• Solid understanding of chip-level integration across advanced technology nodes

• Experience with low-power implementation techniques and UPF

• Proficiency in UNIX scripting (Perl, Python, Tcl, csh, etc.) for flow automation

• Strong debugging skills at functional and gate-level simulation

• Experience with version control systems such as Git

• Good communication skills in English

Why Join

• Opportunity to work on advanced wireless SoC platforms

• Exposure to leading-edge technology nodes and complex mixed-signal environments

• Collaborative and technically strong engineering culture

• Stable and long-term development opportunities within a global organisation