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Digital IC Design Engineer (TPE)

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Divided into 5 teams with different JD as below:

#1

【Job Description】

  1. Digital IC design
  2. Low power design
  3. RTL coding/simulation
  4. SoC integration
  5. FPGA/IC verification

【Requirement】

  1. Accumulated 3 years+ digital IC design related experience.
  2. Familiar with Verilog RTL coding/simulation
  3. Familiar with 28nm/12nm or advanced process
  4. Familiar with low power methodology
  5. Familiar with FPGA verification
  6. Experience in AXI/APB protocol or advanced AMBA bus is preferred
  7. Experience in PCIe SSD is preferred
  8. Experience in NVMe/DMA/bus design is preferred
  9. Experience in SoC integration is preferred

#2

【Job Description】

  1. Maintain USB3.2/SATA/PCIe MAC Mass Production ICs and issue tracking/debugging
  2. Integrate USB3.2/USB4/SATA/PCIe related IPs
  3. Analysis, design and verify USB3.2/USB4/SATA/PCIe clk_rst, DMA datapath and peripheral functions
  4. Support USB3.2/USB4/SATA/PCIe link compliance test and PHY electrical test
  5. Analysis Spyglass Lint/CDC/RDC report and improve design robustness and code coverage
  6. Maintain and improve ASIC design/verification environment

【Requirement】

  1. Accumulated 2 years+ digital IC design related experience.
  2. 具備USB3.2/SATA/USB4/PCIe相關整合/設計/除錯經驗為佳.
  3. 熟悉SystemVerilog, 具備USB3.2/USB4/PCIe MAC UVM驗證經驗為佳
  4. 熟悉USB3.2/PCIE/SATA/USB4 Compliance Test系統測試環境為佳
  5. 熟悉AXI/APB Bus Protocol
  6. 熟悉Spyglass Lint/CDC/RDC and IMC function coverage tool is a plus
  7. 熟悉perl/makefile/python language is a plus
  8. 具備良好溝通能力

#3

【Job Description】

  1. Digital IC design
  2. RTL coding / simulation
  3. System integration
  4. ASIC/FPGA verification

【Requirement】

  1. Accumulated 3 years+ digital IC design related experience.
  2. Familiar Verilog RTL coding/ simulation.
  3. Familiar with Design Compiler/PrimeTime/Prime Power/Conformal LEC.
  4. Familiar with 28nm/12nm or advanced process.
  5. Experience in FPGA verification.
  6. Experience in AXI/AHB/APB protocol is a plus.
  7. Experience in DMA is preferred.
  8. Experience in encryption/decryption IP (AES/SHA/RSA/etc …) is preferred.

#4

【Job Description】

1.Digital IC designer

2.RTL coding/simulation

3.ASIC front-end design flow development

4.Familiar with Physical Design EDA tools

5.SOC / IP synthesis, DFT, STA and timing closure

【Requirement】

1.Accumulated 3 years+ digital IC design related experience.

2. Familiar with Verilog / TCL / Perl / shell script / makefile

3.Familiar with Design Compiler: DCG synthesis / Floorplanning / low power flow

4.Familiar DFT flow: OCC/ Scan compression / ATPG / BSD / Memory BIST

5.Familiar with Prime Time: STA / PTPX / Timing closure flow

6.Familiar with Conformal: LEC / CLP

7.Familiar with 28nm or advanced process

8.Experience in the Tessent MBIST flow is preferred.

#5

【Job Description】

  1. Digital IC design
  2. RTL coding / simulation
  3. FPGA/Emulator platform integration and implement

【Requirement】

1.Accumulated 3 years+ digital IC design related experience.

2. Familiar with Verilog RTL coding/ simulation

3.Familiar with Perl / makefile / shell script

4.Familiar with FPGA or emulator integration and implement

5.Experience in PCIe/USB SSD platform is preferred.

6.Experience in USB3.2/USB4/SATA/PCIe is preferred.

7.Experience in NAND control is preferred.

#6

【Job Description】

1.Digital IC designer

2.RTL coding/simulation

3.Low power design.

【Requirement】

1.Accumulated 3 years+ digital IC design related experience.

2. Familiar with Verilog / SystemVerilog

3.Familiar with TCL / Perl / shell script

4.Familiar with NAND/ONFI/TOGGLE Spec.

5.Experience in ECC/LDPC is preferred.

#7

【Job Description】

  1. RTL/Digital circuit design, synthesis, and simulation/verification.
  2. FPGA synthesis, verification.
  3. SOC architecture development & integration, algorithm implementation.
  4. High speed Serdes IO design & verification.

【Requirement】

  1. Accumulated 3 years+ digital IC design related experience.
  2. Familiar with complete ASIC design flow, UPF, and EDA tools (DCG synthesis, at-speed scan insertion, modern memory bist insertion and STA)
  3. Experience in ASIC/FPGA integration (ARM CPU architecture, AXI/APB bus protocol, Clock/Reset structure, Xilinx FPGA/HAPS implement).
  4. Familiar with DDR system architecture & integration or High-speed I/O protocol such as PCIe and USB.
  5. SOC DFT and Low-power implementation experience are a plus.

Contract Type: FULL_TIME

Specialism: Semiconductor

Focus: Digital IC Design

Industry: Engineering

Salary: Negotiable

Workplace Type: On-site

Experience Level: Associate

Location: Taipei

Job Reference: 1TKN7W-A050FBE2

Date posted: 28 May 2024

Consultant: Joanne Chen

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