Sr. DFT Engineer

Seeking a Senior Design Engineer specializing in Front-End and DFT Implementation for next-generation wireless Mixed-Signal SoCs. You will drive synthesis, DFT circuits, and power optimization (PPA) using advanced nodes (22nm and below). This role requires proactive leadership in a cross-functional environment to deliver high-performance silicon solutions.

Technical Leadership & Flow Development

• Lead the front-end and DFT design implementation for wireless SoC projects.

• Develop and optimize low-power implementation methodologies, including Synthesis, STA, and timing/power closure.

• Improve PPA (Power, Performance, Area) across advanced technology nodes (22nm and below).

Synthesis & DFT Implementation

• Execute and optimize Synthesis, Formal Verification, and Static Timing Analysis (STA).

• Drive the full DFT lifecycle: Integration planning, implementation, and verification (SCAN, ATPG, MBIST).

• Implement front-end low-power strategies using UPF (Unified Power Format).

Cross-functional Collaboration

• Work closely with Digital, Analog, and Physical Design teams to refine RTL-to-Netlist flows.

• Interface with Product, Test Engineering, and global design organizations to ensure seamless SOC development.