Senior Design Verification Engineer

About the Role Join a leading technology company in Hsinchu as a Design Verification Engineer and take part in verifying high-performance SerDes PHY IP. You will work with a collaborative team, using advanced verification methodologies and tools, while enjoying flexible work arrangements, training programs, and a culture that values growth and knowledge sharing.

Key Responsibilities

• Develop UVM-based verification environments and testbenches for SerDes PHY IP.

• Analyse specifications, define verification plans, and create coverage-driven strategies.

• Build/evaluate verification IP, generate constraint-random tests, and perform coverage analysis.

• Collaborate with analog PHY teams on co-simulation and integration validation.

• Document verification process and contribute to continuous improvement.

What We’re Looking For

• 3–5+ years of ASIC/IC design or verification experience.

• Strong knowledge of UVM/OVM/VMM, functional & code coverage techniques.

• Experience verifying SerDes PHY IP or high-speed protocols (PCIE, USB, MPHY, CPHY, DPHY).

• Ability to create/evaluate VIPs and write verification plans.

• Excellent collaboration and documentation skills.

Why Join Us

• Work with top experts in a supportive, knowledge-sharing environment.

• Access flexible work options and continuous learning opportunities.

• Contribute to industry-leading products and grow with a company that invests in its people.

Apply Now

Ready to advance your career in digital design verification? Apply today and be part of a team that values excellence and collaboration.