Design Verification Engineer (WLB)

About the Role Our client is seeking a highly skilled DV Engineer to join their dynamic team in Hsinchu. This role provides an exciting opportunity to contribute to top-level or sub-block pre-silicon design verification, covering all aspects from test plan definition to verification coverage analysis. You will work with state-of-the-art methodologies, including SystemVerilog and UVM, while collaborating closely with the validation team to support post-silicon debugging. If you're looking for a challenging and rewarding opportunity in semiconductor verification, this role is for you!

Key Responsibilities

• Define test plans for top-level or sub-block pre-silicon design verification.
• Develop test environments using SystemVerilog (SV) / UVM + C.
• Create test cases for design verification.
• Implement functional coverage coding and perform verification coverage analysis.
• Collaborate with the validation team to support post-silicon debugging.
• Utilize programming skills in Perl, Python, and C/C++ for verification tasks.

What You Bring

• 2+ years of experience in semiconductor design verification.
• Strong proficiency in SystemVerilog and OVM/UVM/VMM for testbench development.
• Experience developing stimulus, checkers, assertions, and functional coverage.
• Hands-on experience with Perl, Python, and C/C++ for automation and scripting.
• Strong analytical and debugging skills to resolve verification challenges efficiently.

Why Join Us?

Our client is a leading innovator in the semiconductor industry, known for its commitment to technological excellence and employee growth. They offer:

• A collaborative and supportive work environment that fosters leadership and professional development.
• Cutting-edge technology and methodologies to keep you at the forefront of the industry.
• A strong innovation culture, providing the opportunity to make a significant impact in semiconductor design.

Next Steps

Are you ready to advance your career with this exciting DV Engineer opportunity?

DM: joanne.chen@robertwalters.com.tw or Line: joanne454j