Design Verification Engineer

Keywords: Digital Design, Verification, Engineer, UVM, ASIC/IC Verification About the Role: Join a leading technology company in Hsinchu as a Design Verification Engineer. This role involves working on cutting-edge digital design projects, focusing on serdes phy IP using UVM. You will play a significant role in the verification of digital designs, from standard spec study and design feature study to co-simulation with analog phy.

Key Responsibilities:

• Verify digital designs, focusing on serdes phy IP using UVM.
• Conduct standard spec studies and design feature studies.
• Create simple VIP or survey third-party VIPs.
• Define Vplan and build SB/assertion checks.
• Stimulus creation using constraint random techniques.
• Develop covergroup/assertion cover for functional coverage.
• Ensure code coverage.
• Perform co-simulation with analog phy.

Qualifications:

• 3-5+ years of experience in ASIC/IC verification or design.
• Familiarity with UVM/OVM/VMM/ERMDV.
• Experience with PCIE, USB, MPHY, CPHY, DPHY products is preferred.
• Strong understanding of digital design principles.
• Excellent problem-solving skills and attention to detail.
• Ability to work collaboratively within a team.
• Effective multitasking and priority management skills.

What Sets This Company Apart:
Join a top technology company known for innovation and excellence. They offer a supportive, collaborative work environment with excellent career progression opportunities and a commitment to professional development.

What's Next:
Ready to advance your career? Apply now by clicking the link!