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Staff Design Verification Engineer (Hybrid)

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Our client is seeking a seasoned Design Verification Engineer to join their rapidly expanding Semiconductor business. This role offers an exciting opportunity to work in a high-performing, fast-paced global environment. The successful candidate will be responsible for defining testbench infrastructure, digital level verification, and chip level verification of mixed signal IC. This role provides the chance to work closely with the design team to architect new design verification environments and produce high-quality verification closure. * Opportunity to work in a fast-paced, high-performing global business * Responsibility for complete digital and chip level verification * Chance to collaborate with the design team on new verification environments

What you'll do:

As a Design Verification Engineer, your role will be pivotal in driving the success of our client's semiconductor business. You will define testbench infrastructure using System Verilog, UVM and Formal, taking full responsibility for complete digital level verification. Your expertise will also be required in modelling analog functions in System Verilog and ensuring complete chip level verification of mixed signal IC. Collaborating closely with the design team, you will architect new design verification environments and produce high-quality verification closure. Additionally, you will contribute to infrastructure work by developing scripts, methodologies and tools that enhance efficiency and quality.

  • Define testbench infrastructure using System Verilog, UVM and Formal
  • Take responsibility for complete digital level verification
  • Model analog functions in System Verilog
  • Be responsible for chip level verification of mixed signal IC
  • Work closely with the design team to architect a new design verification environment
  • Produce high quality verification closure
  • Develop scripts, methodologies and tools for efficiency and quality improvements

What you bring:

The ideal candidate for the Design Verification Engineer role brings a wealth of experience in ASIC/IC verification. You have honed your skills over 10+ years in the industry and are adept at UVM based verification flow. Your understanding of OOP concepts is solid and you are familiar with scripting languages such as Make file, Perl, TCL or Python. Experience with Sim Vision or Verdi debug skills would be beneficial. If you have experience in Assertion and formal verification (Jasper, 0-in, IFV, Model checking), it would be considered a significant advantage.

  • Over 10 years of experience in ASIC/IC verification.
  • Proficient in UVM-based verification methodologies.
  • Strong understanding of Object-Oriented Programming (OOP) concepts.
  • Familiar with scripting languages such as Makefile, Perl, TCL, or Python.
  • Skilled in using debug tools - SimVision, Verdi, etc.
  • Experience with assertion-based and formal verification techniques (e.g., Jasper, 0-in, IFV, or Model Checking) is an added advantage.

What sets this company apart:

Our client is committed to driving innovation within their industry through their comprehensive portfolio of microcontrollers, analog and power devices. Their mission is to develop a safer, healthier, greener, and smarter world by providing intelligence to their four focus growth segments: Automotive, Industrial, Infrastructure, and IoT. They are dedicated to creating a diverse culture where everyone is included and feels a sense of belonging. The company's culture is built on five key elements: 'Transparent, Agile, Global, Innovative, Entrepreneurial.' These elements form the foundation for a flexible response to changes, problem-solving capabilities, and sustainable value creation.

What's next:

Ready to take the next step in your career? Apply now!

Apply today by clicking on the link provided. We look forward to receiving your application!

Contract Type: FULL_TIME

Specialism: Semiconductor

Focus: Design Verification

Industry: Engineering

Salary: TWD2,500,000 - TWD3,700,000 per annum

Workplace Type: Hybrid

Experience Level: Associate

Location: Hsinchu City

Job Reference: JRP9JW-01A729F2

Date posted: 03 October 2024

Consultant: Joanne Chen

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