Design Verification Engineer

Keywords: SystemVerilog, UVM, C/C++, Integration test environment, VIP, checker and scoreboard development, SystemVerilog assertion, Test plan An exciting opportunity has arisen for a Design Verification Engineer to join a leading technology company. This role is perfect for someone who thrives in a dynamic, fast-paced environment and has a passion for technology. The successful candidate will be responsible for design verification with SystemVerilog/UVM, C/C++, integration test environment with VIP, developing checker and scoreboard, and verifying design with SystemVerilog assertion. This is an excellent opportunity to work on cutting-edge technology projects and develop your skills in a supportive and inclusive environment.

About the Role:

1. Conduct design verification using SystemVerilog/UVM, C/C++.
2. Develop an integration test environment using VIP (Verification IP).
3. Create checkers and scoreboards for verification.
4. Verify the design using SystemVerilog assertions.
5. Develop a comprehensive test plan for verification tasks.

Required Qualifications:

1. Proficient in SystemVerilog HDL, Object-Oriented Programming (OOP), Python, TCL, and shell programming.
2. Preferred background in System-on-Chip (SoC) design and understanding of bus concepts.

Preferred Qualifications:

1. Holds a Master's degree in Electrical Engineering or Computer Science.
   
   

If you're intrigued by the fast-paced environment of startups, my client won't disappoint you. With cutting-edge technology at hand, we'll lead you into the latest generation of AI/Data Center applications.

If you are interested, please contact Joanne directly via Line. (ID: joanne454j)