Our client is seeking a highly skilled and knowledgeable Design Verification Engineer to join their dynamic team. This role offers an exciting opportunity to create verification plans for complex digital design blocks, interact with design engineers, and contribute significantly to the delivery of functionally correct design blocks. The successful candidate will have the chance to work in a supportive and inclusive environment, where they can further develop their skills and make a real impact.
What you'll do:
As a Design Verification Engineer, you will play a crucial role in creating verification plans for complex digital designs. You will be responsible for interacting with design engineers to identify key verification scenarios and creating suitable environments using System Verilog, SystemC or UVM. Your excellent problem-solving skills will be essential in identifying and writing coverage measures for various scenarios. Furthermore, you will collaborate closely with design engineers to debug tests and ensure the delivery of functionally correct design blocks. Your commitment to closing coverage measures will be instrumental in identifying verification gaps and demonstrating progress towards tape-out.
- Creating verification plans of complex digital design blocks by fully understanding the design specification.
- Interacting with design engineers to identify important verification scenarios.
- Creating verification environments using System Verilog, SystemC or UVM.
- Identifying and writing all types of coverage measures for stimulus and corner-cases.
- Debugging tests with design engineers to deliver functionally correct design blocks.
- Closing coverage measures to identify verification holes and show progress towards tape-out.
What you bring:
The ideal candidate for this Design Verification Engineer role will bring a strong educational background in Electrical Engineering or Computer Science. Your experience in verifying digital logic at the Register Transfer Level (RTL) using System Verilog or SystemC for ASICs and/or SoCs will be highly valued. Additionally, your familiarity with creating and using verification components and environments in a standard verification methodology such as UVM, OVM, or VMM will set you apart. A Master’s degree in electrical engineering or computer science would be advantageous.
- Bachelor's degree in Electrical Engineering or Computer Science.
- Experience in verifying digital logic at the Register Transfer Level (RTL) using System Verilog or SystemC for ASICs and/or SoCs.
- Experience with the creation of and usage of verification components and environments in a standard verification methodology such as UVM, OVM, or VMM.
- Preferred: Master’s degree in electrical engineering or computer science.
What sets this company apart:
Our client is renowned for its commitment to innovation and excellence. They offer a supportive and inclusive work environment where every team member is valued for their unique contributions. They believe in fostering growth through continuous learning and offer numerous opportunities for professional development. Their commitment to work-life balance is demonstrated through their flexible working arrangements.
What's next:
If you are a passionate Design Verification Engineer looking to make an impact, this is the opportunity for you!
Apply today by clicking on the link. We look forward to receiving your application!
