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Design Verification Engineer

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Our client is one of the most potential start-up in current IP area. They hold a great techniques and provide amazing customised service and products to their clients. With a stable clients' source, they are still expanding their team to fulfil strong demand and traget to become the best one in the market.

About the Role:

  1. Conduct design verification using SystemVerilog/UVM, C/C++.
  2. Develop an integration test environment using VIP (Verification IP).
  3. Create checkers and scoreboards for verification.
  4. Verify the design using SystemVerilog assertions.
  5. Develop a comprehensive test plan for verification tasks.

Required Qualifications:

  1. Proficient in SystemVerilog HDL, Object-Oriented Programming (OOP), Python, TCL, and shell programming.
  2. Preferred background in System-on-Chip (SoC) design and understanding of bus concepts.

Preferred Qualifications:

  1. Holds a Master's degree in Electrical Engineering or Computer Science.

If you're intrigued by the fast-paced environment of startups, my client won't disappoint you. With cutting-edge technology at hand, we'll lead you into the latest generation of AI/Data Center applications.

If you are interested, please contact Joanne directly via Line. (ID: joanne454j)

Contract Type: FULL_TIME

Specialism: Semiconductor

Focus: Design Verification

Industry: Engineering

Salary: Negotiable

Workplace Type: On-site

Experience Level: Associate

Location: Hsinchu City

Job Reference: R49JAT-3DB9AB4B

Date posted: 04 June 2024

Consultant: Joanne Chen

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