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Design Verification Engineer

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The Role: As a Design Verification Engineer, you will collaborate with CPU designers, compiler teams, performance teams, and system verification teams to automatically generate test cases that meet various verification requirements. Your main focus will be on establishing a random instruction test generator that produces self-checking direct test cases.

Responsibilities:

  • Design, develop, document, and deploy random instruction generators to support multiple projects.
  • Support the execution of the generator and flows within the RTL design process.
  • Integrate and enhance an existing instruction-level verification flow.

Qualifications:

  • Bachelor's or Master's degree in Computer Science, Electrical Engineering, or a related field.
  • Familiarity or academic experience with hardware design and verification.
  • Experience with basic CPU micro-architecture, functional verification, and simulation tools.
  • Proficiency in software project architecture/design and programming in Python or C++11 and above.
  • Basic understanding of Verilog, System-Verilog RTL, UVM, and constraint random verification.

Contract Type: FULL_TIME

Specialism: Semiconductor

Focus: Design Verification

Industry: Engineering

Salary: Negotiable

Workplace Type: Hybrid

Experience Level: Associate

Location: Hsinchu City

Job Reference: DV04NQ-DCE4BDB0

Date posted: 04 June 2024

Consultant: Joanne Chen

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