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Design Verification Engineer (Central Flow)

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e are seeking a candidate with extensive and in-depth experience in digital verification (DV), preferably with a background as a Project DV leader/manager. Additionally, experience in writing verification IPs (VIPs) and conducting thorough verification of relatively complex protocols would be highly desirable. Also, those who has strong knowledge of advanced IP would be highly preferred as well.

The Role:

  1. Develop and maintain the central DV flow.
  2. Collaborate with the design team and DV team to assess new DV flow.
  3. Debug and analyze unit/block/whole-chip verification environments.
  4. Provide technical consulting on various verification methodologies.

What We Are Looking For:

[Mandatory Requirements]

  1. 8+ years of related working experience.
  2. Hands-on experience in whole-chip test bench setup.
  3. Hands-on experience on high-speed IO protocols verification, like PCIe, USB3, USB4, DDR4, LPDDR4.
  4. Proficiency in verification methodologies such as UVM, VMM, or OVM.
  5. Familiarity with Verilog/SystemVerilog and script languages.

[Additional Preferences]

  1. Familiarity with constrained random verification.
  2. Familiarity with assertion-based verification.
  3. Familiar with low power verification
  4. Familiarity with Synopsys Zebu/HAPS or Cadence Palladium/Protium.



If you are interested in this role, please do not hesitate to contact Joanne via her line. (ID: joanne454j)

Contract Type: FULL_TIME

Specialism: Semiconductor

Focus: Design Verification

Industry: Engineering

Salary: Negotiable

Workplace Type: On-site

Experience Level: Associate

Location: Hsinchu City

Job Reference: 1RBIT2-982F38DE

Date posted: 29 May 2024

Consultant: Joanne Chen

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