Physical Design Engineer

Seeking a PD Engineer for Netlist-to-GDSII flow. You will drive the full design cycle on advanced nodes to meet PPA targets. Key tasks include floorplanning, STA, and physical verification. You will develop Tcl/Perl scripts to automate flows. Expertise in major EDA tools for complex SoC delivery is required.

Core Responsibilities

• Full-Flow Implementation: Lead the complete physical design path (Netlist-to-GDSII), including Floorplanning, Power Planning, Placement, Clock Tree Synthesis (CTS), and Routing.

• Timing Convergence: Conduct rigorous Static Timing Analysis (STA) to identify and resolve complex timing violations across all PVT corners and modes.

• Physical Verification & Sign-off: Execute and clear DRC, LVS, and ERC to ensure the design meets all foundry requirements and is ready for tape-out.

• Power & Reliability Engineering: Implement advanced low-power methodologies (multi-voltage, power gating) and perform detailed IR drop and Electromigration (EM) analysis.

• Signal Integrity Management: Detect and mitigate signal integrity issues such as crosstalk and noise to ensure robust high-speed performance.

• Workflow Automation: Build and maintain robust automation environments using Tcl, Shell, Perl, or Makefiles to drive engineering productivity.

Technical Skills & Tools

• Synthesis & Implementation: Proficiency in leading industry tools for RTL synthesis and physical implementation (e.g., Fusion Compiler or ICC2).

• Timing & Analysis: Expertise in industry-standard sign-off tools for timing analysis, parasitic extraction, and power integrity (e.g., PrimeTime, StarRC, Redhawk).

• Physical Verification: Advanced skills in layout verification platforms (e.g., Calibre).

• Programming: Highly skilled in scripting for design flow automation (Tcl/Perl/Shell).