We are currently seeking an experienced Senior Analog Design Manager/ Engineer with a focus on SerDes technology. The ideal candidate should possess a minimum of 5 years of relevant experience, and project leadership experience is highly desirable.
At least 5 years of experience in analog design.
Preferred experience in leading projects.
Strong expertise in RX design; TX design experience is a plus; familiarity with PLL is also considered.
Educational background: Master's degree in electrical engineering.
Previous management experience is highly valued.
Candidates aspiring to accumulate team management experience are encouraged to apply, and corresponding managerial roles can be arranged.
High-Speed Expertise: Proficient in high-speed analog design, specifically in PAM4.
Financial Stability: Our company's investors include a prominent publicly listed IC design firm in Taiwan, signifying a robust financial condition for our organization.
Diverse Applications: The role involves working on cutting-edge applications, including automotive and server high-speed transmission, providing a dynamic and challenging work environment.
If you are a seasoned analog designer with a strong background in SerDes technology and possess or aspire to gain management experience, we invite you to apply.
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Our client is one of the leading domestic Tier 1 Driver IC design house, renowned for its significant achievements in driving ICs of various sizes, as well as touch technologies. We are currently seeking candidates with 3-8 years of relevant experience or seasoned professionals with over 10 years of experience to join our team. Exceptional candidates may have the opportunity to advance into potential management roles based on their performance.
Our client is one of the most potential start-up in current IP area. They hold a great techniques and provide amazing customised service and products to their clients. With a stable clients' source, they are still expanding their team to fulfil strong demand and traget to become the best one in the market.
About the Role:
1 Conduct design verification using SystemVerilog/UVM, C/C++.
2 Develop an integration test environment using VIP (Verification IP).
3 Create checkers and scoreboards for verification.
4 Verify the design using SystemVerilog assertions.
5 Develop a comprehensive test plan for verification tasks.
1 Proficient in SystemVerilog HDL, Object-Oriented Programming (OOP), Python, TCL, and shell programming.
2 Preferred background in System-on-Chip (SoC) design and understanding of bus concepts.
1 Holds a Master's degree in Electrical Engineering or Computer Science.